Executive Certification in RISC-V IP Verification
About the Course:
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor.
This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn CPU architecture, RISC-V IP Verification using SystemVerilog and UVM, ASIC Verification Methodologies, Formal Verification, Low Power Verification, Portable Stimulus Standard, with various Case Studies.
In this course you will verify a multi-stage RISC-V Pipeline Processor – exploring RTL IP verification using formal verification, SystemVerilog, UVM, and RISC-V CPU compliance testing. This project experience will help you deal with verifying any complex RISC-V CPUs and IPs, and creating Verification IPs.
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Program Fee
Rs 1,50,000 + GST
Available Seats
100
Schedule
9 Months
Only Few Seats Left
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Module 1
RISC-V Processor Architecture
- RISC-V Overview
- RISC-V ISA - Base ISA, RV32I Instructions, Extensions
- RISC-V Privilege Levels
- Machine ISA
- Supervisor ISA
- Hypervisor ISA
- PMA, PMP
Module 2
RISC-V Debug
- Introduction to RISC-V Debug
- RISC-V Debug System
- RISC-V Debug Control and Status Registers [ CSR's ]
- Debug Process
Module 3
RISC-V PLIC
- Introduction to Platform Level Interrupt Controller [ PLIC ]
- PLIC Operations and Various Registers
Module 4
RISC-V Software Interfaces and Programming
- Application Binary Interface [ ABI ]
- Supervisor Binary Interface [ SBI ]
- RISC-V Assembly Programming
- RISC-V Toolchain
- Demo on RISC-V toolchain flow
Module 5
Caches
- Memory Hierarchy
- Locality of reference
- Cache Associativity
- Cache Policies
- Cache Coherency Protocols
Module 6
Virtual Memory Management
- Introduction to Virtual Memory
- Address Translation and Page Table Walk
- Translation Lookaside Buffer [ TLB ]
Module 7
CPU Architecture and Pipelined Design
- Basics of CPU and role in a computing system
- RISC vs. CISC architectures
- Instruction Set Architecture (ISA) overview
- Components of a CPU
- Memory hierarchy interaction
- Instruction Execution Cycle
- Pipelined Design
- Hazards in Pipelining
- Advanced Pipelining Techniques
- Performance Analysis
Module 8
RISC-V Processor IP RTL Verification
- RISC-V RV32I RTL Architecture Design
- RISC-V RV32I 5 Stage Pipelined RTL Design
Module 9
Advanced Verilog and Code Coverage
- Timescale System Task
- Generate Blocks
- Self-checking Testbench
- Named Events
- Verilog Stratified Event Queue
- Statement Coverage
- Branch Coverage
- Toggle Coverage
- Finite State Machine Coverage
- Hands-On Labs
Module 10
ASIC Verification Methodology
- Verification Essentials
- DV concepts and flow
- Testplan
- Directed Vs Random Testcases
- Constraint Random Coverage Driven Verification [ CRCDV ]
Module 11
SystemVerilog HVL
- SystemVerilog Datatypes
- SystemVerilog Memories
- SystemVerilog Tasks & Functions
- Object Oriented Programming - Basic
- Object Oriented Programming - Advanced
- SV Randomization
- SV Threads, Mailbox and Semaphores
- SV Virtual Interfaces
- Functional Coverage
- Case Studies
- Hands-On Labs
Module 12
SystemVerilog Assertions
- Different types of Assertions
- Sequences
- Different Operators & Sequence Compositions
- Definition of reusable Sequences and Properties
- Connecting Assertions to DUT
- SVA Coverage and Control Tasks
- Hands-On Labs
Module 13
Formal Verification
- Emergence of Formal Verification
- Formal Verification Algorithms
- Formal Property Verification
- Formal Equivalance Checking
- Types of Equivalence Checking
- Hands-On Labs
Module 14
Universal Verification Methodology [ UVM ]
- UVM Overview
- UVM TB Architecture and Base Class Hierarchy
- UVM Factory
- Stimulus Modelling & Testbench Overview
- UVM Phases and Reporting Mechanism
- TLM Ports and Configuration
- Creation of UVM TB Components
- UVM Sequences
- Virtual Sequences & Virtual Sequencers
- UVM Events & Callbacks
- Creating Scoreboard in UVM
- Hands-On Labs
Module 15
Low Power Verification [ LPV ]
- Necessity of Low Power
- Unified Power Format [ UPF ]
- Modeling Power Intent in UPF
- Static Low Power Verification with UPF
- Dynamic Low Power verification with UPF
- Advanced UPF-Based Verification
- Hands-On Labs
Module 16
Portable Stimulus Standard [ PSS ]
- PSS Basics
- PSS Constructs
- Test Scenario Modeling
- Coverage in PSS
- Integration with Verification Methodologies
- Advanced PSS Concepts
- Case Study
Module 17
RISC-V ISA Compliance
- Compliance Test framework
- Running Compliance Tests
Module 18
Gen AI for VLSI
- Introduction to Gen AI
- Large Language Models
- Prompt Engineering
- Model Fine Tuning and Domain-based models for VLSI
- Gen AI for VLSI
- ML for EDA
Module 19
Business communication
- Transition from College to Corporate
- Interpersonal Skills and Presentation Skills
- Email Etiquette
- Resume Writing
- Mock Interviews: Technical/HR
- Interview Skills: Group Discussion
- and HR Round Preparation
NEWS & UPDATES
Career Transitions
55% Average Salary Hike
$1,27,000 Highest Salary
800+ Career Transitions
300+ Hiring Partners
Who Can Apply for the Course?
- Anyone with a bachelor’s degree and a passion for VLSI
- Professionals looking to grow their career in VLSI
- Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
- Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
- Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout
About Program
At iHUB DivyaSampark, we are driven by the belief that young, innovative minds have immense potential to transform the world. Our core mission is to develop highly knowledgeable human resources with top-order, industry-relevant skills.
Whether you are looking for a career transition, a significant salary hike, or to master specialized knowledge, our programs provide the mentorship and practical exposure needed to achieve successful career outcomes and help you secure roles with our network of 300+ hiring partners
Key Highlights
Our Alumni Work At
What is included in this course?
- Non-biased career guidance
- Counselling based on your skills and preference
- No repetitive calls, only as per convenience
- Rigorous curriculum designed by industry experts
- Complete this program while you work
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