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Module 1

VLSI SoC Design

• VLSI Technology Overview
• Moore’s Law
• IP, Subsystems, and Chips
• SoC Architecture
• SoC Design Process
• System-Level Design - Hardware & Software
• Semiconductor Industry Overview

Module 2

SoC ASIC Design Flow

• VLSI Design Flow
• ASIC Vs FPGA

Module 3

SoC Design - Methodology, Process & Fabrication

• Microcontrollers Vs Complex SoCs
• Computer System Architecture - Von Neuman Vs Harvard
• SoC Design Considerations
• RISC-V ISA Overview
• RISC-V Toolchain
• Memories - Physical Vs Virtual
• MMUs and Interrupt Controllers

Module 4

Memories and Memory Controllers

• Introduction to Memories
• Volatile Memories
• Non-Volatile Memories
• Memory Controllers

Module 5

Caches

• Memory Hierarchy
• Locality of reference
• Cache Associativity
• Cache Policies
• Cache Coherency Protocols

Module 6

Operating Systems

Features of OS

Module 7

Virtual Memory Management

•  Introduction to Virtual Memory
•  Address Translation and Page Table Walk
•  Translation Lookaside Buffer [ TLB ]

Module 8

RISC-V Processor Architecture

• RISC-V Overview
• RISC-V ISA -  Base ISA, RV32I Instrcutions, Extensions
• RISC-V Privilege Levels
• Machine ISA
• Supervisor ISA
• Hypervisor ISA
• PMA, PMP

Module 9

RISC-V Debug

• Introduction to RISC-V Debug
• RISC-V Debug System
• RISC-V Debug Control and Status Registers [ CSR's ]
• Debug Process

Module 10

RISC-V PLIC

• Introduction to Platform Level Interrupt Controller [ PLIC ]
• PLIC Operations and Various Registers

Module 11

RISC-V Software Interfaces and Programming

•  Application Binary Interface [ ABI ]
•  Supervisor Binary Interface [ SBI ]
•  RISC-V Assembly Programming
•  RISC-V Toolchain
•  Demo on RISC-V toolchain flow

Module 12

RISC-V Processor IP RTL Design and Verification

• RISC-V RV32I RTL Architecture Design
•  RISC-V RV32I 5 Stage Pipelined RTL Design

Module 13

Verilog HDL

• Introduction to EDA tools
•  Data Types
•  Verilog Operators
•  Advanced Verilog for Verification
•  Assignments
•  Synthesis Coding Styles
•  Finite State Machine
•  Hands-On Labs

Module 14

SystemVerilog HVL

• SystemVerilog Datatypes
•  SystemVerilog Memories
•  SystemVerilog Tasks & Functions
•  Object Oriented Programming  - Basic
•  Object Oriented Programming - Advanced
•  SV Randomization
•  SV Threads, Mailbox and Semaphores
•  SV Virtual Interfaces
•  Functional Coverage
•  Case Studies
•  Hands-On Labs

Module 15

Universal Verification Methodology [ UVM ]

• UVM Overview
•  UVM TB Architecture and Base  Class Hierarchy
•  UVM Factory
•  Stimulus Modelling & Testbench Overview
•  UVM Phases and Reporting Mechanism
•  TLM Ports and Configuration
•  Creation of UVM TB Components
•  UVM Sequences
•  Virtual Sequences & Virtual Sequencers
•  UVM Events & Callbacks
•  Creating Scoreboard in UVM
•  Hands-On Labs 

Module 16

ARM Architecture

• ARM Registers
•  ARM Instruction Set Architecture
•  ARM Exceptions and Handling
•  ARM Secure and Non-Secure Models
•  ISA Extensions
•  ARM Memory Model

Module 17

ARM Debug

• ARM Debug Interfaces
•  Debug features
•  Trace and Monitoring
•  Secure and Non-Secure Debug

Module 18

ARM Software Interfaces and Programming

• Introduction to Procedure Call Standards
•  ARM software interfaces with Operating Systems

Module 19

AMBA Protocols

• Advanced eXtensible Bus [ AXI ]
•  Advanced High-Performance bus  [ AHB ]
•  Advnaced Peripheral Bus [ APB ]
•  Coherency Hub Int

Module 20

SoC External Interfaces

• Universal Asynchronous Receiver Transmitter [ UART ]
•  Serial Peripheral Interface [ SPI ]
•  Inter-Integrated Circuit [ I2C ]
•  General Purpose Input Output [ GPIO ]
•  Joint Test Action Group [ JT

Module 21

Low Power Design and Verification

• Sources of Power Consumption
•  Different Techniques for Lowering Power Consumption
•  Transistor resizing
•  Clock Gating
•  Necessity of Low Power
•  Unified Power Format [ UPF ]
•  Modeling Power Intent
•  Static Low Power Verification
•  Dynamic Low Power verification
•  Advanced UPF-Based Verification
•  Hands-On Labs 

Module 22

Business communication

• Transition from College to Corporate
• Interpersonal Skills and Presentation Skills
• Email Etiquette
• Resume Writing
• Mock Interviews: Technical/HR
• Interview Skills: Group Discussion and HR Round Preparation

Module 23

Gate Level Simulation [ GLS ]

• GLS Timing Verification
•  GLS TB Setup and Environment
•  SDF Annotation
•  GLS Overhead
•  Improving GLS Performance
•  GLS Simulation Debugging
•  GLS Regression and Verification Signoff
•  Case Study 

Module 24

C Programming

• Basics of C
•  Control Flow and Loops
•  Strings
•  Pointers
•  Arrays
•  Functions
•  Structures and unions
•  Linked Lists
•  Accessing Registers
•  Hands-On Lab

Module 25

Portable Stimulus Standard [ PSS ]

• PSS Basics
•  PSS Constructs
•  Test Scenario Modeling
•  Coverage in PSS
•  Integration with Verification Methodologies
•  Advanced PSS Concepts
•  Case Study

Module 26

Python for DV Automation

• Python Programming Basics
•  Python Fundamentals for DV
•  Python for Regression Testing
•  Log Parsing and Report Generation
•  Case Study

Module 27

Gen AI for VLSI

• Introduction to Gen AI
• Large Language Models
• Prompt Engineering
• Model Fine Tuning and Domain-based models for VLSI
• Gen AI for VLSI
• ML for EDA 

Module 28

Case Study

• Microchip Polarfire SoC - RISC-V SoC on FPGA