Course Details

Learn from IIT Faculty, Industry Experts & Campus Immersion at IIT Roorkee* (T/C Apply).

Executive Certification in RISC-V IP Design

About the Course:

In today’s AI era, chip designers have access to AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V Open ISA, enabling them to design powerful, innovative SoCs efficiently. With these advancements, even the most complex SoCs can be realized for next-generation electronic products. However, thorough verification is critical to ensure the success of newly designed chips and systems. This makes it the perfect time for chip designers and VLSI enthusiasts to delve into ASIC verification methodologies and learn how to verify IPs, subsystems, and complete SoCs effectively.
The course covers the complete spectrum of VLSI verification skills, starting with ASIC verification methodologies. It progresses to Advanced Verilog, Code Coverage, SystemVerilog, SystemVerilog Assertions (SVA), followed by Formal Verification, including FPV, formal algorithms, equivalence checking, with detailed case studies.
The course then explores UVM - covering TB architecture, factory, phases, TLM Ports, sequences, virtual sequences and RAL, Gate-Level Simulation (GLS), Timing Verification, SDF annotation, Debugging, regression, low-power verification with UPF, Portable Stimulus Standard (PSS) for test scenario modelling, SoC verification methodology with various case studies. In addition, it also covers Python for DV automation, C programming for writing firmware SoC testcases, and Generative AI for RTL design and verification - empowering engineers with AI-assisted design and verification capabilities
This hands-on course ensures that the participants build strong foundations in Design Verification – functional verification, low-power and formal verification, GLS, DV automation, and SoC verification, while gaining hands-on expertise through labs, case studies, and real-world verification projects.

Our Students Rate This Course

4.5

Trainer

MAVEN silicon

Program Fee

Rs 1,50,000 + GST

Available Seats

100

Schedule

9 Months

Only Few Seats Left

All certificate images are for illustrative purposes only and may be subject to change at the discretion of the iHUB - IIT Roorkee.

What is included in this course?

Program Certificate form iHUB DivyaSampark, IIT Roorkee
Live & Self Paced learning for better engagement
No repetitive calls, only as per convenience
Opportunity to meet your mentors through Campus Immersion
25+ hand-on project with integrated labs

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Testimonials

Module 1

RISC-V Processor Architecture

RISC-V Overview
RISC-V ISA - Base ISA, RV32I Instructions, Extensions
RISC-V Privilege Levels
Machine ISA
Supervisor ISA
Hypervisor ISA
PMA, PMP

Module 2

RISC-V Debug

Introduction to RISC-V Debug
RISC-V Debug System
RISC-V Debug Control and Status Registers [ CSR's ]
Debug Process

Module 3

RISC-V PLIC

Introduction to Platform Level Interrupt Controller [ PLIC ]
PLIC Operations and Various Registers

Module 4

RISC-V Software Interfaces and Programming

Application Binary Interface [ ABI ]
Supervisor Binary Interface [ SBI ]
RISC-V Assembly Programming
RISC-V Toolchain
Demo on RISC-V toolchain flow

Module 5

Caches

Memory Hierarchy
Locality of reference
Cache Associativity
Cache Policies
Cache Coherency Protocols

Module 6

Virtual Memory Management

Introduction to Virtual Memory
Address Translation and Page Table Walk
Translation Lookaside Buffer [ TLB ]

Module 7

CPU Architecture and Pipelined Design

Basics of CPU and role in a computing system
RISC vs. CISC architectures
Instruction Set Architecture (ISA) overview
Components of a CPU
Memory Hierarchy Interaction
Instruction Execution Cycle
Pipelined Design
Hazards in Pipelining
Advanced Pipelining Techniques
Performance Analysis

Module 8

RISC-V Processor IP RTL Design

RISC-V RV32I RTL Architecture Design
RISC-V RV32I 5 Stage Pipelined RTL Design

Module 9

Verilog HDL

Introduction to EDA tools
Data Types
Verilog Operators
Advanced Verilog for Verification
Assignments
Synthesis Coding Styles
Finite State Machine
Hands-On Labs

Module 10

Advanced Verilog and Code Coverage

Timescale System Task
Generate Blocks
Self-checking Testbench
Named Events
Verilog Stratified Event Queue
Statement Coverage
Branch Coverage
Toggle Coverage
Finite State Machine Coverage
Hands-On Labs

Module 11

RTL Linting

Introduction to RTL Linting
Coding Guidelines and Standards
Common RTL Lint Checks
Hands-On Labs

Module 12

Logic Synthesis

Introduction to Logic Synthesis
Constraints and Timing
Optimization Techniques
Hands-On Labs

Module 13

Logic Equivalance Checking

Logic Equivalance Checking Flow
Constraints Handling
Equivalance Checking Methodology
Hands-On Labs

Module 14

Clock Domain Crossing

Introduction to Clock Domain Crossing [ CDC ]
Different types of Synchronizers
CDC Analysis
Types of CDC errors
CDC Verification flow
Case Study

Module 15

Reset Domain Crossing

Introduction to Reset Domain Crossing [ RDC ]
RDC Hazards and Issues
RDC Verification Techniques
Case Study

Module 16

Low Power Design

Sources of Power Consumption
Different Techniques for Lowering Power Consumption
Transistor resizing
Clock Gating
Sleep Transistors
Transistor reordering
Dynamic Voltage/Frequency Scaling
Isolation Cells and Level Shifters
Precomputation
Power Oriented Programming
Low Power Design Methodology (UPF)
Hands-On Labs

Module 17

SystemVerilog for RTL Design

Data Types
Operators
Procedural Blocks
Procedural Statements
Tasks and Functions
Packages
Arrays
Interfaces
Hands-On Labs

Module 18

ASIC Verification Methodology

Verification Essentials
DV concepts and flow
Testplan
Directed Vs Random Testcases
Constraint Random Coverage Driven Verification [ CRCDV ]

Module 19

SystemVerilog Assertions

Different types of Assertions
Sequences
Different Operators & Sequence Compositions
Definition of reusable Sequences and Properties
Connecting Assertions to DUT
SVA Coverage and Control Tasks
Hands-On Labs

Module 20

Formal Verification

Emergence of Formal Verification
Formal Verification Algorithms
Formal Property Verification
Formal Equivalance Checking
Types of Equivalence Checking
Hands-On Labs

Module 21

Gen AI for VLSI

Introduction to Gen AI
Large Language Models
Prompt Engineering
Model Fine Tuning and Domain-based models for VLSI
Gen AI for VLSI
ML for EDA

Module 22

Business communication

Transition from College to Corporate
Interpersonal Skills and Presentation Skills
Email Etiquette
Resume Writing
Mock Interviews: Technical/HR
Interview Skills: Group Discussion
and HR Round Preparation

NEWS & UPDATES

Career Transitions

55% Average Salary Hike

$1,27,000 Highest Salary

800+ Career Transitions

300+ Hiring Partners

Who Can Apply for the Course?

Anyone with a bachelor’s degree and a passion for VLSI
Professionals looking to grow their career in VLSI
Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout

About Program

At iHUB DivyaSampark, we are driven by the belief that young, innovative minds have immense potential to transform the world. Our core mission is to develop highly knowledgeable human resources with top-order, industry-relevant skills.
Whether you are looking for a career transition, a significant salary hike, or to master specialized knowledge, our programs provide the mentorship and practical exposure needed to achieve successful career outcomes and help you secure roles with our network of 300+ hiring partners