Hero Image

Executive Certification in Physical Design

About the Course:

In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing solutions like RISC-V to design powerful SoCs efficiently. With these advancements, even the most complex SoCs can be implemented for next-generation electronic products. However, achieving timing closure, power optimization, and area efficiency in physical design is critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Physical Design methodologies—covering the complete flow from RTL to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, routing, timing analysis, power optimization, and sign-off techniques for successful tape-outs.

This course provides a comprehensive foundation in VLSI Physical design and verification. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming – coding styles, FSM design, and lab exercises. It then walks you through device physics and CMOS fundamentals including MOSFET operation, CMOS fabrication, and circuit layout.

The DFT module covers verification testing, ATPG, scan insertion, and fault modelling, while automation skills are developed with Tcl and Python scripting. Students also learn version control with Git, before progressing to the ASIC physical design flow, including floor planning, placement, CTS, routing, STA, layout compaction, and physical verification (DRC, LVS, IR drop, EM). Advanced topics such as signal integrity, low-power verification with UPF, and power-aware checks are included, ensuring learners gain end-to-end expertise from RTL coding to Chip tapeout with strong hands-on exposure through structured labs and industry-aligned projects.



Our Students Rate This Course

4.5
Trainer

MAVEN silicon

Program Fee

Rs 2,00,000 + GST

Available Seats

100

Schedule

9 Months

Only Few Seats Left

Reviews

Testimonials

Module 1

VLSI SoC Design

  • VLSI Technology Overview
  • Moore’s Law
  • IP, Subsystems, and Chips
  • SoC Architecture
  • SoC Design Process
  • System-Level Design - Hardware & Software
  • Semiconductor Industry Overview

Module 2

SoC ASIC Design Flow

  • VLSI Design Flow
  • ASIC Vs FPGA

Module 3

Advanced Digital Design

  • Number Systems
  • Logic Gates
  • Designing Combinational Logic Circuits
  • Latches, Flipflops and Flipflop Conversions
  • Registers & Counters
  • Frequency Dividers
  • Finite State Machines
  • Mealy & Moore FSMs
  • Sequential circuits using Finite State Machines
  • Memories and Programmable Logic Devices.
  • Asynchronous Sequential Circuits

Module 4

RISC-V Instruction Set Architecture

  • RISC-V processor overview
  • RISC-V ISA overview
  • RV32I – R Type Instruction
  • RV32I – I Type Instruction
  • RV32I – S & B Type Instructions
  • RV-32I – J & U Type Instructions
  • RV32I – Assembly programs

Module 5

Linux Operating System

  • Different types of Operating System
  • Design Features & layers
  • Basic Linux commands
  • Advanced commands
  • Utilities
  • Vi editor
  • Networking in Linux
  • Hands-On Labs

Module 6

Verilog HDL

  • Introduction to Verilog HDL
  • Introduction to EDA tools
  • Data Types
  • Verilog Operators
  • Advanced Verilog for Verification
  • Assignments
  • Synthesis Coding Styles
  • Finite State Machine
  • Hands-On Labs

Module 7

CMOS Fundamentals

  • MOSFET
  • CMOS Fabrication
  • CMOS Characteristics
  • CMOS Circuit Design
  • CMOS Transistor Sizing
  • Stick Diagrams and Layouts
  • Non-Ideal Characteristics
  • Hands-On Labs

Module 8

Design for Testing [ DFT ]

  • Verification vs Testing
  • Faults and Types of Testing
  • Levels of Testing
  • Fault Modelling
  • Fault collapsing
  • Introduction to ATPG
  • Fault classes and simulation
  • Scan Insertion and Test compression
  • Hands-On Labs

Module 9

Tool Command Language [ TCL ]

  • Control Flow Statements
  • Procedures
  • Strings
  • Mathematical Operators
  • Lists
  • Arrays
  • Dictionaries
  • Hands-On Labs

Module 10

Python

  • Datatypes and Operators
  • Functions and Loops
  • Python OOP
  • Exceptions
  • File IO Operations
  • Sequences and Methods
  • Hands-On Labs

Module 11

GIT Version Control System

  • Types of Version Control System [VCS]
  • Git - Basic Workflow
  • Git - Various commands
  • Git - Branching & Merging
  • Git - Configuration
  • Hands-On Labs

Module 12

Physical Design - Overview

  • Design Styles
  • Partitioning
  • Floor planning
  • Placement
  • Clock Tree Synthesis [ CTS ]
  • Routing
  • Static Timing Analysis [ STA ]

Module 13

Physical Synthesis

  • Libraries and PDK's
  • Synthesis

Module 14

Static Timing Analysis [ STA ]

  • Types of Timing Analysis
  • STA in Design Flow
  • Different Timing Parameters
  • Techniques to improve Timing
  • Timing Analysis Procedures
  • Setup & Hold time violations
  • Eliminate Setup & Hold time violations
  • Hands-On Labs

Module 15

Floor Planning

  • Criteria to measure the quality of
  • Floorplans
  • Floorplanning Algorithms
  • Floorplan Steps
  • Qualifying Floorplan
  • Types of Floorplan Techniques
  • Hands-On Labs

Module 16

Placement

  • Placement Process
  • Different Tasks in Placement
  • Goals of Placement
  • Pre-placement
  • Timing Optimization Techniques
  • Qualifying placement Hands-On Labs

Module 17

Clock Tree Synthesis [ CTS ]

  • Sanity Checks
  • CTS Preparations
  • High Fan-out Net Synthesis (HFNS)
  • Vs Clock Tree Synthesis
  • Clock Buffer Vs Normal Buffer?
  • CTS Goals
  • Clock Tree Design Rule Constraints
  • Clock Tree Exceptions
  • Labs on Clock Tree Synthesis Hands-On Labs

Module 18

Routing

  • Goals of Routing
  • Routing Constraints
  • Hands-On Labs

Module 19

Logic Equivalance Checking

  • Logic Equivalance Checking Flow
  • Constraints Handling
  • Equivalance Checking Methodology
  • Hands-On Labs

Module 20

Signal Integrity and Cross-Talk Issues

  • Signal Integrity
  • Concerns addressed by Signal Integrity
  • Factors effecting Signal Intergrity
  • Cross Talk Noise
  • Cross Talk Delay
  • Hands-On Labs

Module 21

Noise Analysis and Layout Compaction

  • Layout Compaction
  • Features
  • Design Style Specific Issues
  • Compaction Algorithms
  • Hands-On Labs

Module 22

Unified Power Format [ UPF ]

  • UPF Fundamentals
  • Modeling Power Intent
  • Static Low Power Verification
  • Dynamic Low Power verification
  • Advanced UPF-Based Verification
  • Hands-On Labs

Module 23

Physical Verification and sign-off

  • Design Rule Check [ DRC ]
  • DRC rules
  • Layout versus Schematic [ LVS ]
  • LVS Issues
  • IR Drop Analysis
  • Electro Migration [ EM ]
  • Methods to fix EM
  • Hands-On Labs

Module 24

Gen AI for VLSI

  • Introduction to Gen AI
  • Large Language Models
  • Prompt Engineering
  • Model Fine Tuning and Domain-based
  • models for VLSI
  • Gen AI for VLSI
  • ML for EDA

Module 25

Business communication

  • Transition from College to Corporate
  • Interpersonal Skills and Presentation Skills
  • Email Etiquette
  • Resume Writing
  • Mock Interviews: Technical/HR
  • Interview Skills: Group Discussion and HR Round Preparation

NEWS & UPDATES

Career Transitions

55% Average Salary Hike

$1,27,000 Highest Salary

800+ Career Transitions

300+ Hiring Partners

Who Can Apply for the Course?

  • Anyone with a bachelor’s degree and a passion for VLSI
  • Professionals looking to grow their career in VLSI
  • Any IT Professional with a bachelor’s degree looking to transition into VLSI design and semiconductor technologies
  • Project/Product Managers aiming to transition into or deepen their understanding of VLSI and chip design
  • Engineers who aspire to use industry-standard EDA tools and build their own chips from concept to layout
Who can aaply

About Program

This program by iHub Divya Sampark, IIT Roorkee helps you gain the data analytics, machine learning, and artificial intelligence skills sought after by top employers.

Key Highlights

2 Days Campus Immersion Program*
Master Classes from IIT Faculty or Industry Experts
Hands-On experience with Real-World Projects
iHUB Divya Sampark, IIT Roorkee Certification
Business Communication (Aptitude & Soft Skill Training)
Career Support Services*
Top 5% students from each batch will get an opportunity to pitch before investors for equity based startup funding*
750+ Hrs of Live Online Immersive Learning Journey
Exploring Cutting-edge Applications of Artificial Intelligence in VLSI – A Key Focus Area
70% Hands On , 30% Theory
Master Classes from IIT Faculty and Industry Experts
Business Communication (Aptitude & Soft Skill Training)
Career Support Services
24/7 EDA Tools Access (Cadence, Synopsis, Siemens )
24/7 Access to e-Learn cloud-based platform
Student Success Support

Our Alumni Work At

Maven Alumni

What is included in this course?

  • Non-biased career guidance
  • Counselling based on your skills and preference
  • No repetitive calls, only as per convenience
  • Rigorous curriculum designed by industry experts
  • Complete this program while you work

I’m Interested in This Program